In general, an SRAM semiconductor memory device is faster and easier to use than a Dynamic Random Access Memory (DRAM) device. Because of this, SRAM devices are widely used in applications requiring small and medium sized memory capacity.
The memory cell of a conventional SRAM device consists of two flip-flop circuits consisting of two transmission transistors, two driving transistors, and two load elements. The memory information is preserved as a voltage difference between the input and output terminals of the flip-flops as an accumulated charge. The charge is constantly maintained by a continuous power source applied through the load elements, so a refresh function which is required in a DRAM device is unnecessary in an SRAM device.
The conventional SRAM device comprises either a MOS transistor or a resistor as the load elements. In some instances a depletion type NMOS transistor is used as the load element. However, because it consumes a relatively large amount of power it is not often used in the memory cells of SRAM devices.
Often used for the load elements is an easily made layer of high resistance polycrystalline silicon. The polycrystalline silicon layer consumes a lower amount of power and is therefore conventionally preferred as a load element over NMOS transistors. However, the use of the polycrystalline layer reduces the production yield of the SRAM devices because as the designs of SRAM devices create larger memory capacity, the difference between the current through the load element of a memory cell and the leakage current in the node decreases. The decrease in this ratio of currents degrades the memory retention in the memory cell.
In SRAM devices constructed using CMOS technology, PMOS thin film transistors are used as load elements to reduce this problem, however the problem still exists. The preferred CMOS SRAM devices with PMOS TFT load elements have a low leakage current when in the OFF-state (V.sub.ds =-5 V, V.sub.gs =0 V) to result in a low standby current, and have a high ON/OFF current ratio to improve the memory retention in the memory cell. The better these characteristics in the SRAM device, the more the SRAM device can be integrated for a larger memory capacity.
An SRAM device having a TFT load element with an offset region formed between the gate and drain regions is proposed in a paper entitled "A 0.1-.mu.A Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM" by Manabu Ando, et al., IEEE SC-24, P1708, 1989. According to the Ando paper, the OFF-current of a TFT results from the leakage current of the p-n junction in the drain region. The OFF-current increases as the electric field between the gate and drain regions increases. Therefore, an offset region is formed in the drain region to decrease the electric field between the gate and drain regions. As a result, the OFF-current of the TFT is decreased. The Ando paper also discusses the characteristics of the ON/OFF current in relation to the length of the offset region.
The hot carrier effect in a PMOS TFT load element having an offset structure between the gate and drain regions is reported in a paper entitled "Hot-Carrier Induced Ion/Ioff Improvement of Offset PMOS TFT" by Hiroshi Furuta, et al., 1991, published in the "Symposium on VLSI Technology" at page 27. The Furuta paper proposes the formation of a PMOS TFT load element having an offset region doped with boron using a photo mask.
The attached FIG. 1 is a schematic view of the structure disclosed in Furuta. A gate electrode 12 and source and drain pad electrodes 13 for source and drain regions are formed a predetermined distance from the gate electrode 12 on an insulating layer 11 by depositing and patterning polycrystalline silicon. A gate oxide film 14 is then formed over the gate electrode 12 and the source and drain pad electrodes 13 to form an insulating layer.
A silicon layer is then deposited over the entire resultant surface of the gate oxide film 14 and exposed source and drain electrode pads 13. A channel region 15 is formed in the silicon layer by doping a phosphorus ion using a photo mask. The source 18 and drain regions 16 are formed by doping a BF.sub.2 ion at the ends of the channel region 15. An offset region X is formed in the silicon layer between the channel region 15 and the drain region 16 by a doped boron ion using a photo mask.
An insulating layer 17 is then formed over the entire resultant surface of the silicon layer.
If the offset region X is formed in a PMOS TFT by a doped P.sup.- type impurity, the electric field around the drain junction relaxes and the resistance of the offset region X decreases. As a result, the OFF-current of the TFT is decreased and the ON-current of the TFT is increased.
However, the conventional structure of the memory cell of an SRAM device forces the offset region X of the PMOS TFT to be located on an arbitrary layer which has an electrical potential rather than on a ground potential layer. Therefore, an insulating film must be formed between the offset region X and the arbitrary layer, resulting in an unstable device. The conventional structure also results in a design of an SRAM device in which it is difficult to decrease the OFF-current and difficult to raise the ON-current. In addition, the formation of an offset region X by a doped P type impurity requires the use of an additional photo mask. Further, the effect of the offset region X is reduced by the electrical potential of the layer beneath the offset region X.